Name
Abstract | ||
|---|---|---|
This paper presents a high-throughput memory-efficient decoder architecture for Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes in the high-rate wireless personal area network applications. Two novel techniques which can apply to our selected QC-LDPC codes are proposed, including four-parallel block layered decoding architecture and simplification of the switch networks. The proposed architecture based on a block parallel decoding scheme replaces a crossbar-based interconnect network with a fixed wire network for a switch network. In addition, two-stage pipelining is used to improve the clock speed. A 672-bit, rate-1/2 LDPC decoder is implemented using 90 nm CMOS technology. The design achieves an information throughput of 1.45 Gbps at a clock speed of 285 MHz with a maximum of 16 iterations. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5937812 | 2011 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) |
Keywords | Field | DocType |
belief propagation,computer architecture,working group,ldpc code,cmos technology,forward error correction,low density parity check,throughput,high throughput,decoding,switch network,millimeter wave,cmos integrated circuits,error correction | Personal area network,Computer science,Low-density parity-check code,Network switch,Electronic engineering,Soft-decision decoder,Throughput,Crossbar switch,Clock rate,Memory architecture | Conference |
ISSN | Citations | PageRank |
0271-4302 | 0 | 0.34 |
References | Authors | |
4 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kyung-Il Baek | 1 | 0 | 0.34 |
| Hanho Lee | 2 | 205 | 40.92 |
| Changseok Choi | 3 | 33 | 7.39 |
| Sangmin Kim | 4 | 99 | 16.39 |
| Gerald E. Sobelman | 5 | 225 | 44.78 |