Name
Abstract | ||
|---|---|---|
In this paper, we present an efficient fixed-size systolic array for Montgomery's modular multiplication. The array is designed by the LPGS (Locally Parallel Globally Sequential) partition method [14] and can perform efficiently modular multiplication for the input data with arbitrary bits. Also, we address a computation pipelining technique, which improves the throughput and minimizes the buffer size used. With the analysis of VHDL simulation, we discuss a gap between a theoretical optimal number of partition and an empirical one. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1007/3-540-48686-0_44 | COCOON |
Keywords | Field | DocType |
theoretical optimal number,partition method,input data,efficient fixed-size systolic array,parallel globally sequential,arbitrary bit,modular multiplication,computation pipelining technique,buffer size,vhdl simulation,systolic array | Pipeline (computing),Modular arithmetic,Computer science,Parallel computing,Systolic array,Combinatorial optimization,VHDL,Throughput,Partition (number theory),Computation | Conference |
ISBN | Citations | PageRank |
3-540-66200-6 | 0 | 0.34 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sungwoo Lee | 1 | 61 | 14.50 |
| Hyun-sung Kim | 2 | 247 | 27.36 |
| JungJoon Kim | 3 | 1 | 1.03 |
| Tae-geun Kim | 4 | 9 | 3.02 |
| keeyoung yoo | 5 | 1131 | 120.89 |