Paper Info
Title
Dependability Evaluation Of Time Triggered Architecture Using Simulation
Abstract
The method presented in this paper uses a generic C-language written simulation model of an embedded distributed computer system aimed for a safety-critical control application. The considered system is built using Time Triggered Architecture (TTA) concepts. The aim of the presented simulation method is to evaluate the system capability to tolerate a chosen category of faults. The model, being written in ANSI-C, is portable and machine-independent. Its structure is modular and flexible, so that the system to be studied and the experiment setting can easily be changed. The functionality of this model is demonstrated on a set of fault injection experiments aimed mainly to evaluate the correctness of the Time Triggered Protocol (TTP/C) that implements the abstract concepts of TTA. These experiments were done within the EU/IST project Fault Injection for Time triggered architecture (FIT).
Year
Venue
Keywords
2004
COMPUTING AND INFORMATICS
dependability, simulation, TTA, fault-injection, C-sim
Field
DocType
Volume
Dependability,Computer science,Correctness,Time-Triggered Protocol,Modular design,Time-triggered architecture,Fault injection,Embedded system
Journal
23
Issue
ISSN
Citations 
1
1335-9150
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Stanislav Racek1144.98
Pavel Herout2226.87
Jan Hlavicka38312.76