Abstract | ||
---|---|---|
Transactional Memory (TM) is a promising paradigm for parallel programming. TM allows a thread to make a series of memory accesses as a single, atomic, transaction, while avoiding deadlocks, livelocks, and other problems commonly associated with lock-based programming. In this paper we explore Hardware support for TM (HTM). In particular, we explore how HTM can efficiently support transactions of nearly unlimited size. |
Year | DOI | Venue |
---|---|---|
2013 | 10.1016/j.procs.2013.05.190 | Procedia Computer Science |
Keywords | Field | DocType |
Hardware,Transactional Memory,HTM,TM,Parallel,Concurrent,High-Performance | Lock (computer science),Computer science,Deadlock,Parallel computing,Thread (computing),Transactional memory,Database transaction,Operating system | Conference |
Volume | ISSN | Citations |
18 | 1877-0509 | 0 |
PageRank | References | Authors |
0.34 | 11 | 5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Sasa Tomic | 1 | 8 | 3.24 |
Ege Akpinar | 2 | 0 | 0.34 |
Adrián Cristal | 3 | 424 | 40.74 |
Osman S. Unsal | 4 | 575 | 55.65 |
Mateo Valero | 5 | 4520 | 355.94 |