Name
Title | ||
|---|---|---|
High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules |
Abstract | ||
|---|---|---|
In this paper we present an approach to high-level synthesis of digital circuits from synchronous modules. The synthesiser
implemented takes as its input a functional description of the circuit in the form of a netlist using predefined functional
modules with desired parameters, and produces an AHDL description as an intermediate circuit representation. The functional
modules can be designs entered and produced using different design entry tools and design compilers. The synthesis allows
hardware resource sharing, variable data path widths, variable bit resolutions, and various number representations (e.g. parallel,
serial, stochastic) for different parts of a circuit. As a result of synthesis, pipelined circuit analysis ensures coherent
dataflow through the circuit is produced. At the end, the overall control unit that controls data flow through the circuit
is automatically generated. The synthesiser presents the first part of the implementation of a tool for the optimisation of
circuit design for FPGAs as a target technology.
|
Year | DOI | Venue |
|---|---|---|
1999 | 10.1007/978-3-540-48302-1_41 | FPL |
Keywords | Field | DocType |
high-level hierachical hdl synthesis,pipelined fpga-based circuits,synchronous modules,data flow,digital circuits,resource sharing,circuit design,high level synthesis | Netlist,Digital electronics,Computer science,Circuit extraction,Circuit design,Field-programmable gate array,Real-time computing,Physical design,Electronic circuit,Data flow diagram | Conference |
ISBN | Citations | PageRank |
3-540-66457-2 | 1 | 0.37 |
References | Authors | |
3 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| R. Bruce Maunder | 1 | 14 | 2.62 |
| Zoran Salcic | 2 | 553 | 82.51 |
| George Coghill | 3 | 42 | 5.30 |