Title
A Cross-Layer Technology-Based Study of How Memory Errors Impact System Resilience
Abstract
Highly scaled technologies at and beyond the 22-nm node exhibit increased sensitivity to various scaling-related problems that conspire to reduce the overall reliability of integrated circuits and systems. In prior technology nodes, the assumption was that manufacturing technology was responsible for ensuring device reliability. This basic assumption is no longer tenable. Trying to contain reliability problems purely at the technology level would cause prohibitive increases in power consumption. Thus, a cross-layer approach is required, which spreads the burden of ensuring resilience across multiple levels of the design hierarchy. This article illustrates a methodology for dealing with scaling-related problems via two case studies that link models of low-level technology-related problems to system behavior.
Year
DOI
Venue
2013
10.1109/MM.2013.67
IEEE Micro
Keywords
Field
DocType
prior technology node,impact system resilience,device reliability,technology level,cross-layer technology-based study,scaling-related problem,various scaling-related problem,basic assumption,manufacturing technology,22-nm node exhibit,reliability problem,overall reliability,integrated circuit design,computer architecture,semiconductor devices,data models,resilience
Cross layer,Psychological resilience,Data modeling,Manufacturing technology,Computer science,Parallel computing,Real-time computing,Integrated circuit design,Hierarchy,Integrated circuit,Memory errors
Journal
Volume
Issue
ISSN
33
4
0272-1732
Citations 
PageRank 
References 
12
0.55
8
Authors
8
Name
Order
Citations
PageRank
Veit Kleeberger1573.83
Christina Gimmler-Dumont2574.92
Christian Weis328426.11
Andreas Herkersdorf470388.32
Daniel Mueller-Gritschneder512314.40
Sani R. Nassif62268247.45
Ulf Schlichtmann764570.67
Norbert Wehn81165137.17