Abstract | ||
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This paper presents an efficient architecture for a 4-D eight-phase-shift-keying trellis-coded-modulation (TCM) decoder. First, a low-complexity architecture for the transition metric unit is proposed based on substructure sharing. This scheme significantly reduces the required computation without degrading the performance. Then, a new hybrid T-algorithm for a Viterbi decoder is developed by applying a T-algorithm on both branch metrics (BMs) and path metrics (PMs). TCM encoders usually employ high-rate convolutional codes that yield many more transition paths per state than low-rate codes do. This makes it feasible to purge unnecessary additions by applying the T-algorithm on BMs. Applying the T-algorithm on BMs instead of PMs allows one to move the "search-for-the-optimal" operation out of the add-compare-select-unit (ACSU) loop. Hence, the clock speed will not be affected. In addition, by combining the T-algorithm on BMs and the T-algorithm on PMs, the hybrid T-algorithm can reduce the computations required with the conventional T-algorithm on PMs by as much as 50%. |
Year | DOI | Venue |
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2010 | 10.1109/TVLSI.2009.2015325 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
path metrics,hybrid t-algorithm,efficient 4-d,efficient architecture,required computation,low-complexity architecture,new hybrid t-algorithm,branch metrics,transition metric unit,conventional t-algorithm,viterbi decoder,tcm decoder architecture,trellis coded modulation,clock speed,phase shift keying,codecs,vlsi,convolutional code,logic design,viterbi decoding,convolutional codes | Trellis modulation,Logic synthesis,Convolutional code,Computer science,Real-time computing,Electronic engineering,Viterbi decoder,Encoder,Clock rate,Viterbi algorithm,Branch Metrics | Journal |
Volume | Issue | ISSN |
18 | 5 | 1063-8210 |
Citations | PageRank | References |
5 | 1.14 | 8 |
Authors | ||
3 |
Name | Order | Citations | PageRank |
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Jinjin He | 1 | 11 | 3.11 |
Zhongfeng Wang | 2 | 35 | 4.74 |
Huping Liu | 3 | 5 | 1.14 |