Paper Info
Title
An Interprocedural Parallelizing Compiler and Its Support for Memory Hierarchy Research
Abstract
We present several new compiler techniques employed by our interprocedural parallelizing research compiler, Panorama, to improve loop parallelization and the efficiency of memory references. We first present an overview of the compiler and its associated memory architecture simulation environments. We then present an interprocedural array dataflow analysis, using guarded array regions, for automatic array privatization, an interprocedural static profile analysis, and a graph reduction algorithm for parallel task assignment and data allocation which aims at reducing remote memory references while maintaining loop parallelism.
Year
DOI
Venue
1995
10.1007/BFb0014194
LCPC
Keywords
Field
DocType
memory hierarchy research,interprocedural parallelizing compiler,associative memory
Programming language,Memory hierarchy,Panorama,Computer science,Parallel computing,Compiler,Dataflow,Data allocation,Graph reduction,Remote memory,Memory architecture
Conference
ISBN
Citations 
PageRank 
3-540-60765-X
8
1.10
References 
Authors
24
3
Name
Order
Citations
PageRank
Trung N. Nguyen1243.63
Junjie Gu2536.59
Zhiyuan Li31380155.70