Name
Abstract | ||
|---|---|---|
The weakness of implementation for LDPC encoder is that conventional binary Matrix Vector Multiplier has many clock cycles which lead to limited throughput. In this letter in order to construct efficient architecture, we target on IEEE 802.16e LDPC encoders. Over the standard H matrices with Circulant Permutation Matrices, we propose semi-parallel architecture by using cyclic right shift registers and exclusive-OR instead of complex Matrix Vector Multipliers. Proposed efficient encoder for IEEE 802.16e LDPC satisfies compact size and high throughput. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietfec/e91-a.12.3607 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
LDPC encoder, WiMax, clock cycles, semi-parallel architecture, Circulant Permutation Matrices | Logical matrix,Low-density parity-check code,Matrix (mathematics),Parallel computing,Permutation matrix,Theoretical computer science,Circulant matrix,Encoder,IEEE 802,Throughput,Mathematics | Journal |
Volume | Issue | ISSN |
E91A | 12 | 0916-8508 |
Citations | PageRank | References |
2 | 0.53 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jeong-ki Kim | 1 | 21 | 7.91 |
| Hyunseuk Yoo | 2 | 21 | 3.01 |
| Moon Ho Lee | 3 | 765 | 107.66 |