Paper Info
Title
Memory-, bandwidth-, and power-aware multi-core for a graph database workload
Abstract
Processors have evolved to the now de-facto standard multicore architecture. The continuous advances in technology allow for increased component density, thus resulting in a larger number of cores on the chip. This, in turn, places pressure on the off-chip and pin bandwidth. Large Last-Level Caches (LLC), which are shared among all cores, have been used as a way to control the out-of-chip requests. In this work we focus on analyzing the memory behavior of a modern demanding application, a graph-based database workload, which is representative of future workloads. We analyze the performance of this application for different cache configurations in terms of: memory access time, bandwidth requirements, and power consumption. The experimental results show that the bandwidth requirements reduce as the number of clusters reduces and the LLC per cluster increases. This configuration is also the most power efficient. If on the other hand, memory latency is the dominant factor, assuming bandwidth is not a limitation, then the best configuration is the one with more clusters and smaller LLCs.
Year
DOI
Venue
2011
10.1007/978-3-642-19137-4_15
ARCS
Keywords
Field
DocType
memory latency,best configuration,modern demanding application,power-aware multi-core,large last-level caches,memory behavior,power consumption,larger number,different cache configuration,graph database workload,memory access time,bandwidth requirement,chip,power efficiency,memory bandwidth
Registered memory,Interleaved memory,Memory bandwidth,Uniform memory access,Shared memory,Computer science,Parallel computing,Cache-only memory architecture,Real-time computing,Dynamic bandwidth allocation,Distributed shared memory
Conference
Volume
ISSN
Citations 
6566
0302-9743
0
PageRank 
References 
Authors
0.34
11
3
Name
Order
Citations
PageRank
Pedro Trancoso137743.79
Norbert Martinez-Bazan2484.98
Josep-Lluis Larriba-Pey324521.70