Paper Info
Title
A Novel Low-Cost Multi-Mode Reed Solomon Decoder Design Based on Peterson-Gorenstein-Zierler Algorithm
Abstract
Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Among various Reed-Solomon decoding algorithms, the Peterson-Gorenstein-Zierler (PGZ) algorithm in general has the least computational complexity for small t values. However, unlike the iterative approaches (e.g., Berlekamp-Massey and Euclidean algorithms), it will encounter divided-by-zero problems in solving multiple t values. In this paper, we propose a multi-mode hardware architecture for error numbers ranging from zero to three. We first propose a cost-down technique to reduce the hardware complexity of a t = 3 decoder. A Finite-field Inversion (FFI) elimination scheme is also proposed in our PGZ kernel. Next, we perform an algorithmic-level derivation to identify the configurable feature of our design. With those manipulations, we are able to perform multi-mode RS decoding in one unified VLSI architecture with very simple control scheme. The very low cost and simple data-path make our design a good choice in small-footprint embedded VLSI systems such as Error Control Coding (ECC) in memory/storage systems.
Year
DOI
Venue
2003
10.1023/A:1023200419497
VLSI Signal Processing
Keywords
Field
DocType
Reed-Solomon code,error control coding,Peterson-Gorenstein-Zerler algorithm,Chien search algorithm,Forney algorithm
Computer science,Theoretical computer science,Reed–Solomon error correction,Ranging,Kernel (linear algebra),Parallel computing,Algorithm,Arithmetic,Data integrity,Decoding methods,Forney algorithm,Hardware architecture,Computational complexity theory
Journal
Volume
Issue
ISSN
34
3
0922-5773
Citations 
PageRank 
References 
1
0.42
7
Authors
3
Name
Order
Citations
PageRank
Huai-Yi Hsu1172.27
Sheng-Feng Wang210.75
An-Yeu (Andy) Wu3977.92