Title
Layered Memory Architecture for High IO Intensive Information Services to Achieve Timeliness
Abstract
Storage systems need to provide high IO transactions in addition to their capacity and availability requirements to achieve high assurance characteristics, such as fault tolerance and timeliness. Caches built in large and medium size storage systems have not been very effective to improve the IO transactions and overall performance of the system. Caches at various layers of the memory hierarchy in computing systems are more fast but very small compared to the adjacent lower level of storage device. This paper proposes a novel concept to exploit local memory as a block device to improve the IO performance of storage systems called Data Transmission System (DTS) concept. This concept is based on hierarchical layered memory utilization and management in the information system. Data accessed frequently is maintained on the managed DTS cache device in close proximity to the CPU. The proposed concept is substantially different from the conventional unmanaged cache in the computing systems. System architecture and detailed system design are presented in this paper to realize the proposed concept. Performance evaluation of the system has been carried out through numerical as well as application scenario. The experimental results show improvement of the order of 10 to 100 times faster IO transactions and reduce CPU wait time significantly.
Year
DOI
Venue
2008
10.1109/HASE.2008.42
HASE
Keywords
Field
DocType
io performance,proposed concept,information system,io transaction,high io intensive information,storage system,system architecture,computing system,detailed system design,layered memory,medium size storage system,novel concept,achieve timeliness,write back cache,system design,fault tolerance,data transmission,fault tolerant,indexes,information systems,data access,servers,protocols,iops,locality of reference,information services
Locality of reference,Memory hierarchy,Cache,Computer science,Computer data storage,Systems design,Real-time computing,Fault tolerance,Systems architecture,Memory architecture,Embedded system
Conference
ISSN
Citations 
PageRank 
1530-2059
8
0.63
References 
Authors
4
3
Name
Order
Citations
PageRank
Hironao Takahashi18915.09
Hafiz Farooq Ahmad216429.04
Kinji Mori3450109.20