Name
Abstract | ||
|---|---|---|
In this paper, a new architecture and algorithm for all digital phase-locked loop (ADPLL) is proposed. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator (DCO) structure for low power, small area is presented and its frequency range is from 200 MHz to 750 MHz with a supply voltage 1.2v. The total power consumption of ADPLL is 1.7mW. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption. This ADPLL is designed and implemented by TSMC's 0.13mum CMOS technology |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1693721 | ISCAS |
Keywords | Field | DocType |
uhf detectors,cmos integrated circuits,frequency comparator,all digital phase-locked loop,digital phase locked loops,phase detector,digitally controlled oscillator,low-power electronics,1.7 mw,cmos technology,phase detectors,200 to 750 mhz,1.2 v,uhf oscillators,gain generator,0.13 micron,phase detection,power generation,oscillators,digital control,low power electronics,search algorithm,phase locked loops | Digitally controlled oscillator,Phase-locked loop,Search algorithm,Comparator,Computer science,Voltage,CMOS,Electronic engineering,Phase detector,Electrical engineering,Low-power electronics | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 1 |
PageRank | References | Authors |
0.40 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tzu-chiang Chao | 1 | 1 | 0.40 |
| Wei Hwang | 2 | 254 | 44.40 |