Name
Abstract | ||
|---|---|---|
Regular expression matching has become a critical yet challenging technique in content-aware network processing, such as application identification and deep inspection. To meet the requirement for processing heavy network traffic at line rate, Deterministic Finite Automata (DFA) is widely used to accelerate regular expression matching at the expense of large memory usage. In this paper, we propose a DFA-based algorithm named RCDFA (Reorganized and Compact DFA), which dramatically reduces the memory usage while maintaining fast and deterministic lookup speed. Based on the dissection of real-life DFA tables, we observe that almost every state has multiple similar states, i.e. they share identical next-state transitions for most input characters. However, these similar states often distribute at nonadjacent positions in the original DFA table. RCDFA aims at reorganizing all similar states into adjacent entries, so that identical transitions become consecutive along the state dimension, then compresses the reorganized DFA table utilizing bitmap technique. Coupled with mapping along the character dimension, RCDFA is not only efficient in DFA compression, but also effective for hardware implementation. Experiment results show, RCDFA has superior performance in terms of high processing speed, low memory usage and short preprocessing time. RCDFA consistently achieves over 95% compression ratio for existing real-life rule sets. Implemented in a single Xilinx Virtex-6 FPGA platform, RCDFA matching engine achieved 12Gbps throughput. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/icc.2011.5963291 | ICC |
Keywords | Field | DocType |
finite automata,reorganized and compact dfa,xilinx virtex-6 fpga platform,next state transitions,regular expression matching,computer networks,bitmap technique,content aware network processing,telecommunication traffic,field programmable gate arrays,deterministic finite automata,deep inspection,deterministic finite automata (dfa),regular expression,hardware,pattern matching,state transition,compression ratio,engines,throughput,field programmable gate array,inspection | Regular expression,Deterministic finite automaton,Computer science,Parallel computing,Field-programmable gate array,Computer network,Finite-state machine,Real-time computing,Compression ratio,Preprocessor,Bitmap,Pattern matching | Conference |
Volume | Issue | ISSN |
null | null | 1550-3607 E-ISBN : 978-1-61284-231-8 |
ISBN | Citations | PageRank |
978-1-61284-231-8 | 4 | 0.42 |
References | Authors | |
9 | 4 | |