Name
Abstract | ||
|---|---|---|
In this paper, an Application-Specific Instruction Set Processor (ASIP) -controlled inverse integer transform IP block on a System-on-Chip (SoC) platform is proposed. The proposed design is implemented as an independently operated IP block connected to the ASIP via the Wishbone SoC bus. It features both 4x4 and 8x8 inverse integer transform with additional support for 2x2 and 4x4 Hadamard transforms of DC coefficients. Design portability can be achieved by using the open Wishbone standard for the system bus with a moderate increase in system area. The IP block is controlled by an ASIP which allows functional testability and design flexibility. Compared with existing designs in its class, the circuit area of this design is considerably minimal due to the embodiment of 4x4 circuit in the 8x8 circuit, while achieving a speed of 176MHz. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/RSP.2008.34 | IEEE International Workshop on Rapid System Prototyping |
Keywords | DocType | ISSN |
wishbone soc bus,design flexibility,avc compression,system bus,asip-controlled inverse integer transform,design portability,ip block,system area,circuit area,open wishbone standard,inverse integer,proposed design,instruction sets,application specific instruction set processor,system on a chip,hadamard transform,quantization,data compression,system on chip | Conference | 1074-6005 |
Citations | PageRank | References |
4 | 0.79 | 11 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| N. T. Ngo | 1 | 4 | 0.79 |
| T. T. T. Do | 2 | 4 | 0.79 |
| T. M. Le | 3 | 4 | 0.79 |
| Y. S. Kadam | 4 | 4 | 0.79 |
| A. Bermak | 5 | 35 | 4.72 |