Title
SAT-based synthesis of clock gating functions using 3-valued abstraction
Year
DOI
Venue
2009
10.1109/FMCAD.2009.5351118
FMCAD
Keywords
Field
DocType
boolean functions,data structures,algorithm design and analysis,logic gates,clock gating,digital circuits,sat,network synthesis,functional analysis
Boolean function,Clock gating,Logic gate,Digital electronics,Clock network,Computer science,Network synthesis filters,Clock domain crossing,Parallel computing,Real-time computing,Digital clock manager
Conference
Citations 
PageRank 
References 
6
0.48
23
Authors
3
Name
Order
Citations
PageRank
Eli Arbel1674.23
Oleg Rokhlenko225017.03
Karen Yorav347932.67