Name
Abstract | ||
|---|---|---|
This paper describes an approach to optimise transistor dimensions within a standard cell library. The goal is to extract high-speed and low-power circuits which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. Using statistically enhanced SPICE models based on 3D-atomistic simulations, a genetic algorithm optimises the device widths within a circuit using a multi-objective fitness function. The results show the impact of threshold voltage variation can be reduced by optimising transistor widths, and suggest a similar method could be extended to the optimisation of larger circuits. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/CEC.2009.4983223 | IEEE Congress on Evolutionary Computation |
Keywords | Field | DocType |
random fluctuation,future technology node,variability tolerant standard cell,genetic algorithm,transistor width,multiobjective fitness function,transistor dimension,larger circuit,device width,low-power circuit,spice model,network topology,threshold voltage,data mining,genetic algorithms,design optimization,logic gates,low power electronics,transistors,fitness function,fluctuations,circuit topology,electronics industry | Mathematical optimization,Computer science,Spice,Fitness function,Electronic engineering,Standard cell,Transistor,Electronic circuit,Threshold voltage,Low-power electronics,Topology (electrical circuits) | Conference |
ISBN | Citations | PageRank |
978-1-4244-2959-2 | 7 | 0.62 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| James A. Hilder | 1 | 59 | 6.98 |
| James Alfred Walker | 2 | 250 | 22.94 |
| Andy M. Tyrrell | 3 | 629 | 73.61 |