Name
Abstract | ||
|---|---|---|
After a discussion of the reasons for choosing to implement logic in array form, a detailed description of the nature of array logic is given. Topics specifically discussed include general array structures and implementation, influence of decoder partitioning, design of logic arrays, output phase, “split” variables, feedback in logic arrays, and reconfiguration. |
Year | DOI | Venue |
|---|---|---|
1975 | 10.1147/rd.192.0098 | IBM Journal of Research and Development |
Keywords | Field | DocType |
array logic,general array structure,array form,decoder partitioning,detailed description,logic array,output phase | Logic synthesis,Logic gate,Sequential logic,Logic optimization,Computer science,Programmable logic array,Electronic engineering,Logic family,Register-transfer level,Control reconfiguration | Journal |
Volume | Issue | ISSN |
19 | 2 | 0018-8646 |
Citations | PageRank | References |
80 | 46.54 | 3 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Harold Fleisher | 1 | 98 | 50.37 |
| L. I. Maissel | 2 | 87 | 51.06 |