Name
Title | ||
|---|---|---|
Accelerating FPGA development through the automatic parallel application of standard implementation tools. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/FPT.2010.5681754 | FPT |
Keywords | Field | DocType |
layout,place and route,global change,development environment,routing,viscosity,data structure,logic design,data structures,automatic parallelization,fpga,digital signal processing,modular design,synchronization,field programmable gate arrays,memory bandwidth,white spaces | Logic synthesis,Data structure,Memory bandwidth,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Turnaround time,Modular design,Timing closure,Floorplan,Embedded system | Conference |
Citations | PageRank | References |
4 | 0.49 | 8 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Athira Chandrasekharan | 1 | 4 | 0.49 |
| Sureshwar Rajagopalan | 2 | 4 | 0.49 |
| Guruprasad Subbarayan | 3 | 4 | 0.83 |
| Tony Frangieh | 4 | 4 | 0.49 |
| Yousef Iskander | 5 | 17 | 1.69 |
| Stephen D. Craven | 6 | 15 | 2.36 |
| Cameron D. Patterson | 7 | 59 | 11.71 |