Title
Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Abstract
•SystemC simulation based analysis of the synaptic information distortion in NoC based hardware SNNs.•Fixed spike transfer latency ring topology interconnect for spike communication between neural tiles, using a novel timestamped spike broadcast flow control scheme.•Spike transfer latency results and elimination of information jitter in hardware SNNs.•Micro-architecture of the proposed ring router, FPGA and ASIC synthesis results.•A hierarchical NoC architecture comprising ring topology interconnect within a mesh topology NoC.
Year
DOI
Venue
2013
10.1016/j.parco.2013.04.010
Parallel Computing
Keywords
Field
DocType
Network on Chip (NoC),Spiking Neural Networks (SNN),Synaptic connectivity,Latency jitter
Mesh networking,Computer science,Latency (engineering),Network packet,Parallel computing,SystemC,Packet switching,Jitter,Computer hardware,Ring network,Spiking neural network
Journal
Volume
Issue
ISSN
39
9
0167-8191
Citations 
PageRank 
References 
10
0.51
25
Authors
9
Name
Order
Citations
PageRank
Sandeep Pande1885.92
Fearghal Morgan233634.11
Gerard J. M. Smit388889.18
Tom Bruintjes4242.16
Jochem H. Rutgers5252.63
Brian Mcginley622014.23
Seamus Cawley71108.10
Jim Harkin832536.82
Liam Mcdaid927030.48