Paper Info
Title
Reconfigurable Mesh-Connected Processor Arrays Using Row-Column Bypassing and Direct Replacement
Abstract
This paper proposes an advanced reconfiguration scheme using row-column bypassing and direct replacement for two-dimensional mesh-connected processing-node arrays that makes an array usable for massively parallel computingand stand-alone computing in an efficient dividedmanner. This scheme uses an array providing a switching circuit in every node for row-column by-passing and a simple bypass network with a tree structure allocated to the array by graph-node coloring with a minimum inter-node distance of three for direct replacement. It can reconfigure a subarray with a regular matrix of free nodes usable for parallel computing in the array while allowing a small delay in the meshconnections but maintaining a communication path from every busy node being used as stand-alone computing to the outside of the array. The direct replacement is used for substitution of busy nodes which are not covered by row-column bypassing with free nodes locatedin the rows or columns to be bypassed, helping to enlarge the size of the reconfigured subarray. The bypass allocation with a minimum distance of three enables distributed communications and simple routing in the array while attaining a large success probability of the direct replacement. The proposed scheme is advantageous for constructing fault-tolerant massively parallel systems by using personal computers or workstations as processing nodes and Ethernet devices for interconnections.
Year
DOI
Venue
2000
10.1109/ISPAN.2000.900256
ISPAN
Keywords
Field
DocType
row-column bypassing,array usable,advanced reconfiguration scheme,parallel computing,two-dimensional mesh-connected processing-node array,computingand stand-alone computing,direct replacement,parallel system,reconfigurable mesh-connected processor,busy node,free nodes usable,tree structure,microcomputers,routing,network routing,massively parallel computing,workstations,concurrent computing,matrices,parallel processing,parallel computer,tree data structures,fault tolerant
USable,Row,Massively parallel,Computer science,Tree (data structure),Parallel computing,Ethernet,Tree structure,Concurrent computing,Computer hardware,Control reconfiguration
Conference
ISBN
Citations 
PageRank 
0-7695-0936-3
7
0.54
References 
Authors
6
2
Name
Order
Citations
PageRank
Nobuo Tsuda1246.78
Tatsuyuki Shimizu270.54