Name
Abstract | ||
|---|---|---|
The write performance of the 1.8-V 64-Mb phase-change random access memory (PRAM) has been improved, which was developed based on 0.12-μm CMOS technology. For the improvement of RESET and SET distributions, a cell current regulator scheme and multiple step-down pulse generator were employed, respectively. The read access time and SET write time are 68 ns and 180 ns, respectively. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/JSSC.2005.859016 | Solid-State Circuits, IEEE Journal of |
Keywords | DocType | Volume |
pram,68 ns,phase-change random access memory,phase change materials,random-access storage,set,180 ns,cell current regulator scheme,reset distribution,set distribution,cmos technology,high-speed integrated circuits,multiple step-down pulse generator,1.8 v,64 mbit,pulse generators,phase change,write performance enhancement,distribution,0.12 micron,cmos memory circuits,reset | Journal | 41 |
Issue | ISSN | Citations |
1 | 0018-9200 | 3 |
PageRank | References | Authors |
3.87 | 1 | 13 |