Name
Title | ||
|---|---|---|
Application of Workflow Petri Nets to Modeling of Formal Verification Processes in Design Flow of Digital Integrated Circuits. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/DATE.2008.4484798 | DATE |
Keywords | Field | DocType |
databases,petri net,formal verification,design process,process design,design flow,petri nets,strategic planning,productivity | Formal equivalence checking,Functional verification,Petri net,Systems engineering,Software engineering,Computer science,Intelligent verification,Verification,Real-time computing,Process architecture,High-level verification,Formal verification | Conference |
ISBN | Citations | PageRank |
978-3-9810801-4-8 | 0 | 0.34 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Katharina Weinberger | 1 | 0 | 1.01 |
| Slava Bulach | 2 | 0 | 1.01 |
| Robert Bosch | 3 | 33 | 5.57 |