A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33% - Citegraph

Paper Info

Title
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

Abstract
A 1.8-V embedded 18-Mb DRAM macro with a 9-ns row-address-strobe access time and memory-cell area efficiency of 33% has been successfully developed with a single-side interface architecture, high-speed circuit design, and low-voltage design. In the high-speed circuit design, a multiword redundancy scheme and Y-select merged sense scheme are developed to achieve the performance goal. In the low-vol...

Year	DOI	Venue
2001	10.1109/4.910489	IEEE Journal of Solid-State Circuits
Keywords	DocType	Volume
Random access memory,Capacitors,Circuit synthesis,Latches,Charge pumps,Low voltage,High speed integrated circuits,Integrated circuit noise,Voltage control,Bandwidth	Journal	36
Issue	ISSN	Citations
3	0018-9200	0
PageRank	References	Authors
0.34	1	17

Authors (17 rows)

Cited by (0 rows)

References (1 rows)

Name	Order	Citations	PageRank
Y. Yokoyama	1	0	0.68
N. Itoh	2	0	1.01
M. Hasegawa	3	0	0.34
M. Katayama	4	0	0.68
H. Akasaki	5	0	0.34
M. Kaneda	6	0	0.34
T. Ueda	7	0	0.34
Y. Tanaka	8	3	1.77
E. Yamasaki	9	0	0.34
M. Todokoro	10	0	0.34
K. Toriyama	11	0	0.34
H. Miki	12	0	0.34
M. Yagyu	13	0	0.34
K. Takashima	14	0	0.34
T. Kobayashi	15	39	6.78
S. Miyaoka	16	0	0.34
N. Tamba	17	0	0.34

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