Name
Abstract | ||
|---|---|---|
Prior work on TLB power optimization considered circuit and architectural techniques. A recent software-based technique for data TLBs has considered the possibility of storing the frequently used virtual-to-physical address translations in a set of translation registers (TRs), and using them when necessary instead of going to the data TLB. This paper presents a compiler-based strategy for increasing the effectiveness of TRs. The idea is to restructure the application code in such a fashion that once a TR is loaded, its contents are reused as much as possible. Our experimental evaluation with six array-based benchmarks from the Spec2000 suite indicates that the proposed TR reuse strategy brings significant reductions in data TLB energy over an alternate strategy that employs TRs but does not restructure the code for TR reuse. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/1016720.1016747 | CODES+ISSS |
Keywords | Field | DocType |
performance,power optimization | Power optimization,Suite,Reuse,Computer science,Parallel computing,Real-time computing,Compiler,Software,Translation lookaside buffer,Operating system,Restructuring,Embedded system | Conference |
ISBN | Citations | PageRank |
1-58113-937-3 | 17 | 0.78 |
References | Authors | |
8 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mahmut T. Kandemir | 1 | 7371 | 568.54 |
| Ismail Kadayif | 2 | 611 | 45.50 |
| Guilin Chen | 3 | 92 | 10.54 |