Name
Title | ||
|---|---|---|
Testing the dynamic full access property of a class of multistage interconnection networks |
Abstract | ||
|---|---|---|
The banyan network, and networks topologically equivalent to it, have recently been adopted as interconnection networks in multiprocessor systems. Often, a multiprocessor system is reconfigured when the banyan network becomes faulty. It is possible to avoid a complicated reconfiguration process as long as the faulty banyan network still possesses the dynamic full access (DFA) property. In this paper, we determine a necessary and sufficient condition for a faulty banyan network to possess the DFA property and design a test procedure based on the condition. The test procedure can be used to decompose a faulty banyan network into subsystems possessing the DFA property. We also evaluate the probability that a banyan network loses the DFA property, given the number of faulty switching elements. It is found that as long as faults do not occur in switching elements located in the first and last stages, this probability is very small, even when there are quite a few faulty switching elements |
Year | DOI | Venue |
|---|---|---|
1994 | 10.1109/71.329668 | IEEE Trans. Parallel Distrib. Syst. |
Keywords | Field | DocType |
evaluatethe probability,afaulty banyan network,faulty banyan network,multiprocessor interconnection networks,multistage interconnection networks,necessary andsufficient condition,computer testing,fault tolerant computing,faulty switching element,reconfigurable architectures,network decomposition,interconnection network,test procedure,banyan network,dynamic full access property,dfa property,faulty switching elements,networks topologically equivalent,multiprocessor system reconfiguration,faulty banyan networ,probability,testing,note,fault tolerance,routing,fault detection,fault tolerant | Computer science,Multiprocessing,Multistage interconnection networks,Real-time computing,Fault tolerance,Topological conjugacy,Interconnection,Control reconfiguration,Distributed computing,Banyan network,Test procedures | Journal |
Volume | Issue | ISSN |
5 | 11 | 1045-9219 |
Citations | PageRank | References |
1 | 0.36 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tsern-Huei Lee | 1 | 244 | 30.63 |
| Jin-Jye Chou | 2 | 7 | 1.77 |