Name
Title | ||
|---|---|---|
Prefetching and Multithreading Performance in Bus-Based Multiprocessors with Petri Nets |
Abstract | ||
|---|---|---|
The large latency of memory accesses is a major obstacle in obtaining high processor utilization in large scale shared-memory multiprocessors. Access to remote memory is likely to be slow, compared to the ever-increasing speeds of processors. Thus, any scalable architecture must rely on techniques that can cope with the large latency of memory accesses to reduce/hide/tolerate remote-memory-access latencies. |
Year | DOI | Venue |
|---|---|---|
1997 | 10.1007/BFb0002846 | Euro-Par |
Keywords | Field | DocType |
1. dspn model to hardware-based prefetching,petri nets,bus-based multiprocessors,multithreading performance,petri net | Multithreading,Obstacle,Scalable architecture,Petri net,Computer science,Latency (engineering),Parallel computing,Multiprocessing,Remote memory,Memory module,Distributed computing,Embedded system | Conference |
ISBN | Citations | PageRank |
3-540-63440-1 | 1 | 0.35 |
References | Authors | |
5 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Edward D. Moreno | 1 | 1 | 1.02 |
| Sérgio Takeo Kofuji | 2 | 3 | 1.44 |
| Marcelo H. Cintra | 3 | 72 | 3.42 |