Name
Abstract | ||
|---|---|---|
This paper presents a low-complexity, high-speed 4-dimensional 8-ary Phase Shift Keying Trellis Coded Modulation (4-D 8PSK TCM) decoder. In the design, an efficient architecture for the transition metrics unit (TMU) is proposed to significantly reduce the computation complexity without degrading the performance. In addition, pipelining and parallel processing techniques are exploited to increase the decoding throughput. Synthesis results show that the FPGA implementation of the TCM decoder can achieve a maximum throughput of 1.062 Gbps. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/SIPS.2008.4671765 | SiPS |
Keywords | Field | DocType |
index terms— vlsi,fpga,trellis coded modulation,decoding,parallel processing,phase shift keying,convolution,encoding,modulation,vlsi,computational complexity,4 dimensional,field programmable gate arrays,convolutional codes,indexing terms | Trellis modulation,Pipeline (computing),Convolutional code,Computer science,Real-time computing,Soft-decision decoder,Decoding methods,Throughput,Very-large-scale integration,Phase-shift keying | Conference |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jinjin He | 1 | 11 | 3.11 |
| Zhongfeng Wang | 2 | 59 | 11.49 |
| Huaping Liu | 3 | 504 | 62.29 |