Name
Abstract | ||
|---|---|---|
An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG incorporates an array of 32 x 32 6-bit TSDPC cells along with a 128-word vector memory and occupies 2 x 2 mm(2) in a 65 nm 1.2 V CMOS technology. Digital noise emulation of functional logic cores such as register arrays is demonstrated with chip-level waveform monitoring at power supply, ground, as well as substrate nodes. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transele.E93.C.820 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
noise emulation, substrate noise, power supply noise, signal integrity, substrate coupling, power integrity | Digital electronics,Parasitic capacitance,Signal integrity,Power integrity,Electronic engineering,CMOS,Image noise,Substrate coupling,Engineering,Noise generator,Electrical engineering | Journal |
Volume | Issue | ISSN |
E93C | 6 | 0916-8524 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tetsuro Matsuno | 1 | 26 | 4.50 |
| Daisuke Fujimoto | 2 | 25 | 6.52 |
| Daisuke Kosaka | 3 | 20 | 3.98 |
| Naoyuki Hamanishi | 4 | 14 | 8.16 |
| Ken Tanabe | 5 | 1 | 0.72 |
| Masazumi Shiochi | 6 | 1 | 0.72 |
| Makoto Nagata | 7 | 285 | 76.47 |