Name
Abstract | ||
|---|---|---|
Reducing delay of a digital circuit is an important topic in logic synthesis for standard cells and LUT-based FPGAs. This paper presents a simple, fast, and very efficient synthesis algorithm to improve the delay after technology mapping. The algorithm scales to large designs and is implemented in a publicly-available technology mapper. The code is available online. Experimental results on industrial designs show that the method can improve delay after standard cell mapping by 30% with the increase in area 2.4%, or by 41% with the increase in area by 3.9%, on top of a high-effort synthesis and mapping flow. In a separate experiment, the algorithm was used as part of a complete industrial standard cell design flow, leading to improvements in area and delay after place-and-route. In yet another experiment, the algorithm was applied before FPGA mapping into 4-LUTs, resulting in 16% logic level reduction at the cost of 9% area increase on top of a high-effort mapping.
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Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ICCAD.2011.6105357 | ICCAD |
Keywords | Field | DocType |
area increase,standard cell mapping,complete industrial standard cell,high-effort synthesis,delay optimization,algorithm scale,fpga mapping,sop balancing,efficient synthesis algorithm,technology mapping,mapping flow,high-effort mapping,sram,industrial design,logic synthesis,logic circuits,digital circuits,place and route,simulation,design flow,field programmable gate arrays | Logic synthesis,Lookup table,Logic gate,Digital electronics,Computer science,Field-programmable gate array,Electronic engineering,Real-time computing,Design flow,Standard cell,Logic level | Conference |
ISSN | ISBN | Citations |
1933-7760 | 978-1-4577-1398-9 | 5 |
PageRank | References | Authors |
0.51 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alan Mishchenko | 1 | 982 | 84.79 |
| Robert K. Brayton | 2 | 6224 | 883.32 |
| Stephen Jang | 3 | 96 | 7.91 |
| Victor N. Kravets | 4 | 124 | 11.78 |