Name
Abstract | ||
|---|---|---|
Partitioning is a key database task. In this paper we explore partitioning performance on a chip multiprocessor (CMP) that provides a relatively high degree of on-chip thread-level parallelism. It is therefore important to implement the partitioning algorithm to take advantage of the CMP's parallel execution resources. We identify the coordination of writing partition output as the main challenge in a parallel partitioning implementation and evaluate four techniques for enabling parallel partitioning. We confirm previous work in single threaded partitioning that finds L2 cache misses and translation lookaside buffer misses to be important performance issues, but we now add the management of concurrent threads to this analysis. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1457150.1457156 | DaMoN |
Keywords | Field | DocType |
high degree,important performance issue,chip multiprocessors,partitioning algorithm,parallel partitioning implementation,chip multiprocessor,parallel partitioning,single threaded partitioning,l2 cache,concurrent thread,parallel execution resource,thread level parallelism,data streams,translation lookaside buffer,content addressable memory,chip,network processor | Network processor,Data stream mining,Content-addressable memory,CPU cache,Computer science,Parallel computing,Multiprocessing,Real-time computing,Thread (computing),Translation lookaside buffer,Memory-level parallelism | Conference |
Citations | PageRank | References |
23 | 1.38 | 8 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| John Cieslewicz | 1 | 335 | 19.95 |
| Kenneth A. Ross | 2 | 4110 | 750.80 |