Name
Abstract | ||
|---|---|---|
This paper presents latency and power modeling of an on-chip bus at the early stage of SoC design. The latency model is to estimate a bus throughput associated with bus configuration and behavioral model before the system-level modeling for a target SoC is established. The power model roughly calculates the power consumption of an oh-chip bus including the power consumed by bus wire and bus logics. Thus, the bus architecture is determined by the trade-off between the bus throughput and power estimation obtained from the proposed bus model. We evaluate the target SoCs such as an MPEG player and a portable multimedia player so as to compare the estimated throughput from the proposed bus model to the result performed by a commercial system-level co-simulation framework. As the simulation results, the latency and power consumption of the proposed model shows 14% and 8% differences compared with the result from the validated commercial co-simulation tool. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transele.E93.C.1525 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
on-chip network, performance modeling, power estimation, architecture level modeling, system-on-chip | CAN bus,Power-flow study,IEBus,Electronic engineering,Local bus,Memory bus,Engineering,Back-side bus,System bus,Control bus,Embedded system | Journal |
Volume | Issue | ISSN |
E93C | 10 | 1745-1353 |
Citations | PageRank | References |
2 | 0.36 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyun Lee | 1 | 2 | 0.36 |
| Jehoon Lee | 2 | 37 | 9.61 |
| Kyoung-Rok Cho | 3 | 217 | 31.77 |