Name
Abstract | ||
|---|---|---|
This paper presents a method for evaluating functions based on piecewise polynomial approximations (splines) with a hierarchical segmentation scheme targeting hardware implementation. The methodology provides significant reduction in table size compared to traditional uniform segmentation approaches. The use of hierarchies involving uniform splines and splines with size varying by powers of two is particularly well suited for the coverage of nonlinear regions. The segmentation step is automated and supports user-supplied precision requirements and approximation method. Bit-widths of the coefficients and arithmetic operators are optimized to minimize circuit area and enable a guarantee of 1 unit in the last place (ulp) accuracy at the output. A coefficient transformation technique is also described, which significantly reduces the dynamic ranges of the fixed-point polynomial coefficients. The hierarchical segmentation method is illustrated using a set of functions including -(x/2) log2x, cos-1(x), √-ln(x), a high-degree rational function, ln(1 + x), and 1/(1 + x). Various degree-1 and degree-2 approximation results for precisions between 8 to 24 bits are given. Hardware realizations are demonstrated on a Xilinx Virtex-4 field-programmable gate array (FPGA). |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2008.2003165 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
traditional uniform segmentation approach,hierarchical segmentation scheme,piecewise polynomial approximation,piecewise poly- nomial approximation.,hardware implementation,index terms—circuit synthesis,field-programmable gate arrays fpgas,hardware realization,degree-2 approximation result,fixed-point polynomial coefficient,design automation,digital sys- tems,hierarchical segmentation method,segmentation step,approximation method,hardware function evaluation,rational function,application specific integrated circuits,field programmable gate arrays,logic design,field programmable gate array,arithmetic,fixed point,splines,indexing terms,hardware,fpga,dynamic range,polynomials | Spline (mathematics),Polynomial,Computer science,Segmentation,Unit in the last place,Field-programmable gate array,Electronic engineering,Gate array,Computer hardware,Rational function,Piecewise | Journal |
Volume | Issue | ISSN |
17 | 1 | 1063-8210 |
Citations | PageRank | References |
15 | 0.86 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dong-U Lee | 1 | 380 | 34.15 |
| Ray C. C. Cheung | 2 | 625 | 72.26 |
| Wayne Luk | 3 | 3752 | 438.09 |
| John D. Villasenor | 4 | 855 | 81.44 |