Name
Abstract | ||
|---|---|---|
This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TCSI.2012.2206494 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
sequential circuits,low gate-count,combinational circuits,mux-ff,multiplexing equipment,8-to-1 serializer,transmitters,multiplexer-flip-flops,pipeline,mux-latch,cmos technology,low gate-count pipeline topology,cmos logic circuits,size 90 nm,cascaded latches,flip-flops,4-to-1 mux-ff,serial link transmitters,mux-latches,serial link,multiplexer-latches,logic function,receiver,systems | Serial communication,Topology,Gate count,Sequential logic,FLOPS,Computer science,Multiplexer,CMOS,Electronic engineering,Combinational logic,Serializer | Journal |
Volume | Issue | ISSN |
59 | 11 | 1549-8328 |
Citations | PageRank | References |
6 | 0.55 | 10 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei-Yu Tsai | 1 | 73 | 5.06 |
| Ching-Te Chiu | 2 | 304 | 38.60 |
| Jen-Ming Wu | 3 | 62 | 19.81 |
| Shawn S. H. Hsu | 4 | 29 | 7.01 |
| Yarsun Hsu | 5 | 199 | 39.62 |