Name
Title | ||
|---|---|---|
Glitch-Free Multi-Modulus Frequency Divider for Quantization Noise suppression in fractional-N PLLs |
Abstract | ||
|---|---|---|
A novel frequency divider for Quantization Noise (QN) suppression in fractional-(QN) phase-locked loops (PLLs) is presented in this paper. The proposed Multi-Modulus Frequency Divider (MMFD) utilizes a novel glitch-free divide-by-0.5/1/1.5/2 cell to reduce the frequency division step to 0.5 and the quantization noise induced by ΔΣ modulation is thus suppressed by additional 6dB. The circuit is designed and simulated in a 0.18μm CMOS process. The maximum input frequency is up to 3.8GHz across all variations of Process, supply Voltage and Temperature (PVT) and the current consumption is about 8mA from a 1.8V supply. Compared with other frequency dividers used for QN suppression, the proposed MMFD achieves 6dB QN suppression while consuming less power and operating at higher input frequency. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ISCAS.2011.5937606 | ISCAS |
Keywords | Field | DocType |
cmos process,cmos integrated circuits,δς modulation,fractional-n pll,voltage 1.8 v,quantization noise suppression,delta-sigma modulation,mmfd,phase locked loops,phase-locked loop,glitch-free multimodulus frequency divider,frequency dividers,interference suppression,size 0.18 micron,phase locked loop,quantization noise,delta sigma modulation,noise,computer architecture,phase lock loop | Glitch,Phase-locked loop,Frequency divider,Control theory,Computer science,Frequency multiplier,Electronic engineering,CMOS,Modulation,Delta-sigma modulation,Quantization (signal processing) | Conference |
Volume | Issue | ISSN |
null | null | 0271-4302 E-ISBN : 978-1-4244-9472-9 |
ISBN | Citations | PageRank |
978-1-4244-9472-9 | 2 | 0.41 |
References | Authors | |
4 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaoming Liu | 1 | 4 | 1.82 |
| Jing Jin | 2 | 7 | 5.49 |
| Xi Li | 3 | 2 | 0.41 |
| J. Zhou | 4 | 42 | 20.83 |