Name
Abstract | ||
|---|---|---|
This paper presents an architecture to evaluate the reliability of a system- on-chip (SoC) during its runtime that also accounts for the system's redundancy. We propose to integrate an autonomic layer into the SoC to detect the chip's current condi- tion and instruct appropriate countermeasures. In the autonomic layer, error counters are used to count the number of errors within a fixed time interval. The counters' values accumulate into a global register representing the system's reliability. The ac- cumulation takes into account the series and parallel composition of the system. |
Year | Venue | Keywords |
|---|---|---|
2006 | GI-Jahrestagung | cumulant,system on chip |
Field | DocType | Citations |
Fixed time,Architecture,Computer science,Chip,Redundancy (engineering),Embedded system,Fold (higher-order function) | Conference | 4 |
PageRank | References | Authors |
0.63 | 11 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Andreas Bernauer | 1 | 38 | 4.68 |
| Oliver Bringmann | 2 | 586 | 71.36 |
| Wolfgang Rosenstiel | 3 | 1462 | 212.32 |
| Abdelmajid Bouajila | 4 | 27 | 2.95 |
| Walter Stechele | 5 | 365 | 52.77 |
| Andreas Herkersdorf | 6 | 703 | 88.32 |