Name
Title | ||
|---|---|---|
FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach |
Abstract | ||
|---|---|---|
In this paper we propose a novel area-time efcient archi- tecture for the realization of self-clocked MAC lters on FPGA. First, the self-timed 4-phase oscillator/counter is an- alyzed and characterized, showing experimental results in comparison with simulation foreseen. Next, the proposed lter architecture, based on circular memories, is described and efciently implemented as an IP module using device primitives and relative location constraints. Finally, an ex- ample using the proposed architecture is implemented on an FPGA and compared with a standard IP lter of similar characteristics, pointing out the advantages of our approach. |
Year | Venue | Keywords |
|---|---|---|
2005 | Field-Programmable Logic and Applications | oscillations,fir filter,logic design,fir filters,field programmable gate arrays |
Field | DocType | Citations |
Logic synthesis,Architecture,Computer science,Field-programmable gate array,Real-time computing,Finite impulse response | Conference | 1 |
PageRank | References | Authors |
0.43 | 3 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Javier Martínez | 1 | 35 | 5.78 |
| F. Javier Toledo | 2 | 175 | 18.14 |
| F. Javier Garrigós | 3 | 18 | 4.15 |
| José Manuel Ferrández De Vicente | 4 | 42 | 11.19 |