Name
Abstract | ||
|---|---|---|
This paper presents a 12-bit 200-MS/s dual channel pipeline analog-to-digital converter (ADC). The ADC is featured with a digital timing correction for reducing a sampling skew and the capacitor swapping for suppressing nonlinearities at the first stage in the pipelined ADC. The prototype ADC occupies 0.8x1.4mm^2 in a 65-nm CMOS technology. The differential nonlinearity is less than 1.0 least significant bit with a 200MHz sampling frequency. With a sampling frequency of a 200-MS/s and an input of a 2.4MHz, the ADC, respectively, achieves a signal to noise-and-distortion ratio and a spurious-free dynamic range of 61.49dB-70.71dB while consuming of 112mW at a supply voltage of 1.1V. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1016/j.mejo.2011.08.002 | Microelectronics Journal |
Keywords | Field | DocType |
skew reduction technique,sampling skew,65-nm cmos technology,differential nonlinearity,dual channel pipeline analog-to-digital,sampling frequency,digital timing correction,d converter,pipelined adc,12-bit 200-ms,significant bit,prototype adc,least significant bit,spurious free dynamic range | Differential nonlinearity,Sampling (signal processing),Electronic engineering,Effective number of bits,Sampling (statistics),Skew,Engineering,Successive approximation ADC,Computer hardware,Integrating ADC,Least significant bit | Journal |
Volume | Issue | ISSN |
42 | 11 | 0026-2692 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jae-Won Nam | 1 | 29 | 6.41 |
| Young-Deuk Jeon | 2 | 98 | 13.50 |
| Young-Kyun Cho | 3 | 19 | 5.05 |
| Jong-Kee Kwon | 4 | 158 | 23.10 |