Paper Info
Title
A Flexible VLSI Parallel Processing System for Block-Matching Motion Estimation in Low Bit-Rate Video Coding Applications
Abstract
In this paper, we design a flexible VLSI-based parallel processing system for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
Year
Venue
Keywords
1999
ACPC
low bit-rate video,new three-step search,motion estimation algorithm,block-matching motion estimation,coding applications,h.261 standard,existing three-step search,vlsi tree processor,parallel processing system,three-step search algorithm,improved three-step search,flexible vlsi,itss algorithm,proposed architecture,flexible vlsi-based parallel processing,parallel processing,motion estimation
Field
DocType
Volume
Signal processing,Search algorithm,Computer science,Image processing,Field-programmable gate array,Theoretical computer science,Coding (social sciences),Motion estimation,Very-large-scale integration,Motion vector
Conference
1557
ISSN
ISBN
Citations 
0302-9743
3-540-65641-3
0
PageRank 
References 
Authors
0.34
4
2
Name
Order
Citations
PageRank
D. Xu1116.96
Reza Sotudeh2418.69