Name
Abstract | ||
|---|---|---|
This paper describes the total support system for DDL which has been approved by design engineers at Fujitsu. A simulator is used not only at register transfer level but also with gate level description. The translator generates gate level designs which are then optimized by designers. The verifier has powerful functions to detect conflicts in specification and its implementation.
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Year | DOI | Venue |
|---|---|---|
1979 | 10.1109/DAC.1979.1600137 | DAC |
Keywords | Field | DocType |
design engineer,gate level description,total support system,powerful function,gate level design,large-scale computer,register transfer level,registers,software systems,automatic control,design optimization,power function,feature extraction,computational modeling,logic design | Logic synthesis,Computer aided instruction,Computer architecture,Support system,Computer science,Electronic engineering,Automatic control,Software system,Register-transfer level | Conference |
ISBN | Citations | PageRank |
978-0-89791-020-0 | 14 | 12.78 |
References | Authors | |
2 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nobuaki Kawato | 1 | 105 | 79.03 |
| Takao Saito | 2 | 33 | 24.81 |
| fumihiro maruyama | 3 | 44 | 25.75 |
| Takao Uehara | 4 | 48 | 33.66 |