Paper Info
Title
A 1/2 X Vdd To 3 X Vdd Bidirectional I/O Buffer With A Dynamic Gate Bias Generator
Abstract
This paper presents a wide-range I/O buffer able to transmit and receive signals of 0.9/1.2/1.8/3.3/5.0 V by using a typical 0.18 mu m CMOS process. The Dynamic gate bias circuit in the proposed I/O buffer is composed of two voltage converters, an EOS (Electrical Overstress) protector, and standard logic cells. A High voltage detector detects voltage level of VDDIO and then generates several bias voltages to the Dynamic gate bias circuit. By using the Dynamic gate bias generator to generate appropriate gate drives for the triple-stacked MOS transistors in the Output stage, the gate-oxide overstress and hot-carrier degradation are avoided. A Floating N-well circuit in the proposed I/O buffer is used to remove undesirable leakage current paths. The proposed I/O buffer can operate at 10/40/50/40/10 MHz when VDDIO are biased at 5.0/3.3/1.8/1.2/0.9 V, respectively. The maximum speed is 50 MHz given a 19 pF load. The maximum static power consumption is merely 3.9 mu W justified by the measurements on silicon.
Year
DOI
Venue
2010
10.1109/TCSI.2009.2036054
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Keywords
DocType
Volume
Dynamic gate bias, floating N-well, I/O buffer, mixed-voltage tolerant, wide-range
Journal
57
Issue
ISSN
Citations 
7
1549-8328
0
PageRank 
References 
Authors
0.34
0
3
Name
Order
Citations
PageRank
Chua-chin Wang1474107.39
Chia-Hao Hsu24411.63
Yi-Cheng Liu34113.29