Name
Abstract | ||
|---|---|---|
The number of resources available in the largest reconfigurable devices enables the synthesis of systems with more than 100 Soft-Core processors. Although a feasible and attainable option, few such systems have been built and few published works propose methods to create, program and optimize this kind of system. In this work we present a methodology that helps the designer to build Multi Processor System on Chip (MPSoC) systems based on Network on Chip (NoC) interconnection, and also to develop applications and to analyze their performance. In this methodology several tools have been combined such as SOPC builder from Altera, NoCMaker from UAB, and Vampir from GWT-TUD. As a result, a NoC-based MPSoC consisting of 16 NIOS II Soft-Core processors has been built and successfully tested with several applications. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/ICECS.2010.5724503 | Electronics, Circuits, and Systems |
Keywords | Field | DocType |
microprocessor chips,multiprocessor interconnection networks,network-on-chip,parallel programming,NoCMaker,SOPC builder,Vampir,multiprocessor system on chip system,network on chip interconnection,soft-core processor,FPGA,MPI,MPSoC,NoC,Parallel programming,Performance analysis | Computer architecture,System on a chip,Computer science,Field-programmable gate array,Network on a chip,Soft core,Interconnection,MPSoC,Nios II,Embedded system,Scalability | Conference |
ISBN | Citations | PageRank |
978-1-4244-8155-2 | 4 | 0.57 |
References | Authors | |
9 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eduard Fernandez-Alonso | 1 | 9 | 1.73 |
| David Castells-Rufas | 2 | 45 | 7.70 |
| Sergi Risueño | 3 | 4 | 0.57 |
| Jordi Carrabina | 4 | 139 | 36.98 |
| Jaume Joven | 5 | 38 | 4.27 |
| Fernandez-Alonso, E. | 6 | 4 | 0.57 |
| Castells-Rufas, D. | 7 | 4 | 0.57 |