Name
Abstract | ||
|---|---|---|
We have developed a set of performance prediction tools which help to estimate the achievable speedups from parallelizing a sequential simulation. The tools focus on two important factors in the actual speedup of a parallel simulation program: the simulation protocol used; and the inherent parallelism in the simulation model. The first two tools are a performance/parallelism analyzer for a conservative, asynchronous simulation protocol, and a similar analyzer for a conservative, synchronous (super-step) protocol. Each analyzer allows us to study how the speedup of a model changes with increasing number of processors, when a specific protocol is used. The third tool-a critical path analyzer-gives on ideal upper bound to the model's speedup. This paper gives an overview of the prediction tools, and reports the predictions from applying the tools to a discrete-event wafer fabrication simulation model. The predictions are close to speedups from actual parallel implementations. These tools help us to set realistic expectations of the speedup from a parallel simulation program, and to focus our work on issues which are more likely to yield performance improvement |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/PADS.1999.766171 | Workshop on Parallel and Distributed Simulation |
Keywords | Field | DocType |
parallel processing,discrete event simulation,integrated circuit manufacture,sequential simulation,conservative synchronous simulation,model change,performance improvement,simulation protocol,software performance evaluation,achievable speedup,performance prediction tools,simulation model,actual speedup,conservative asynchronous simulation,asynchronous simulation protocol,critical path analyzer,sequential simulation parallelization,upper bound,discrete-event wafer fabrication simulation,parallel discrete-event simulation,wafer fabrication simulation,parallel simulation program,performance prediction tool,stability,critical path,flow control,manufacturing,context modeling,read only memory,protocols,information systems | Asynchronous communication,Upper and lower bounds,Computer science,Wafer fabrication,Parallel computing,Real-time computing,Critical path method,Performance prediction,Distributed computing,Discrete event simulation,Speedup,Performance improvement | Conference |
ISBN | Citations | PageRank |
0-7695-0155-9 | 10 | 0.76 |
References | Authors | |
10 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chu-Cheow Lim | 1 | 168 | 14.45 |
| Yoke-Hean Low | 2 | 54 | 7.74 |
| Boon-Ping Gan | 3 | 68 | 9.08 |
| Sanjay Jain | 4 | 1647 | 177.87 |
| Wentong Cai | 5 | 1928 | 197.81 |
| Wen Jing Hsu | 6 | 174 | 13.70 |
| Shell Ying Huang | 7 | 161 | 19.52 |