Name
Abstract | ||
|---|---|---|
This paper presents a new microarchitecture technique named DYNAMEM, in which memory reference instructions are dynamically
scheduled and can be executed out-of-order. Load instructions can bypass store instructions speculatively, even if the store
instructions’ addresses are unknown. DYNAMEM can greatly alleviate the restraints of ambiguous memory dependencies. Simulation
results show that the frequency of false load is low. Mechanism has been provided to repair false loads with low penalty,
and to achieve precise interrupts. Discussions and experimental results show that DYNAMEM could dramatically raise instruction-level
parallelism in programs without recompilation. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1007/BF02951622 | J. Comput. Sci. Technol. |
Keywords | Field | DocType |
dynamic scheduling,instruction-level parallelism,memory de- pendency.,out of order | Instruction-level parallelism,Computer science,Parallel computing,Real-time computing,Dynamic priority scheduling,Microarchitecture | Journal |
Volume | Issue | ISSN |
11 | 6 | 1860-4749 |
Citations | PageRank | References |
0 | 0.34 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xianzhu Wang | 1 | 0 | 0.34 |
| Heng Liao | 2 | 21 | 4.16 |
| Sanli Li | 3 | 104 | 15.38 |