Name
Abstract | ||
|---|---|---|
We are focusing on the development of a highly compact neural net weight function based on the use of EEPROM devices. These devices have already proven useful for analog weight storage, but existing designs rely on the use of conventional voltage multiplication as the weight function, requiring additional transistors per synapse. A parasitic capacitance between the floating gate and the drain of the EEPROM structure leads to an unusual J-V characteristic which can be used to advantage in designing a compact synapse. This novel behavior is well characterized by a model we have developed. A single-device circuit results in a 1-quadrant synapse function which is nonlinear, though monotonic. A simple extension employing 2 EEPROMs results in a 2 quadrant function which is much more linear. This approach offers the potential for more than a ten-fold increase in the density of neural net implementations. |
Year | Venue | Keywords |
|---|---|---|
1990 | NIPS | compact eeprom-based weight function,weight function |
Field | DocType | ISBN |
EEPROM,Monotonic function,Mathematical optimization,Parasitic capacitance,Weight function,Nonlinear system,Computer science,Voltage,Electronic engineering,Multiplication,Computer hardware,Transistor | Conference | 1-55860-184-8 |
Citations | PageRank | References |
3 | 0.61 | 1 |
Authors | ||
4 | ||