Name
Title | ||
|---|---|---|
Predicting communication protocol performance on superscalar architectures using instruction dependency |
Abstract | ||
|---|---|---|
Increasing diversity in telecommunication workloads leads to greater complexity in communication protocols. This occurs as channel bandwidth rapidly increases. These factors result in larger computational loads for network processors that are increasingly turning to high performance microprocessor designs. This paper presents an analytical method for estimating the performance of instruction level parallel (ILP) processors executing network protocol processing applications. Instruction dependency information extracted while executing an application is used to calculate upper and lower bounds for throughput, measured in instructions per cycle (IPC). Results using UDP/TCP/IP applications show that the simulated IPC values fall between the analytically derived upper and lower bounds, validating the model. The analytical method is much less expensive than cycle-accurate simulation, but reveals similar throughput performance predictions. This allows the architectural design space for network superscalar processors to be explored more rapidly and comprehensively, to reveal the maximum IPC that is possible for a given application workload and the available hardware resources. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1016/j.peva.2005.10.004 | Perform. Eval. |
Keywords | Field | DocType |
instruction dependency,network protocol processing application,network superscalar processor,predicting communication protocol performance,similar throughput performance prediction,lower bound,simulated ipc value,maximum ipc,high performance microprocessor design,ip application,analytical performance modeling,network processing,superscalar architecture,analytical method,network processor,network protocol,upper and lower bounds,information extraction,communication protocol,instructions per cycle | Instructions per cycle,Network processor,Upper and lower bounds,Computer science,Workload,Parallel computing,Microprocessor,Real-time computing,Throughput,Channel capacity,Communications protocol | Journal |
Volume | Issue | ISSN |
63 | 9 | Performance Evaluation |
Citations | PageRank | References |
2 | 0.38 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tsai Chi Huang | 1 | 4 | 2.38 |
| Linda M Wills | 2 | 293 | 40.95 |
| Roy W. Melton | 3 | 5 | 2.21 |
| Cecil O. Alford | 4 | 27 | 7.87 |