Name
Abstract | ||
|---|---|---|
LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques. |
Year | DOI | Venue |
|---|---|---|
1985 | 10.1109/MDT.1985.294814 | Design & Test of Computers, IEEE |
Keywords | DocType | Volume |
msi circuit,multilevel random logic,logic reorganization system,printed-circuit assembly logic,lsi circuit,logic minimization,target lsi circuit,logic design,lsi logic circuit,original circuit,logic circuits,read only memory,databases | Journal | 2 |
Issue | ISSN | Citations |
5 | 0740-7475 | 4 |
PageRank | References | Authors |
3.15 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kiyoshi Enomoto | 1 | 7 | 5.51 |
| Shunichiro Nakamura | 2 | 17 | 16.12 |
| Takuji Ogihara | 3 | 33 | 11.01 |
| Shinichi Murai | 4 | 50 | 20.89 |