Name
Abstract | ||
|---|---|---|
The need for bridging the ever growing gap between memory and processor performance has motivated research for exploiting the memory hierarchy effectively. An important software solution called code reordering produces a new program layout to better utilize the available memory hierarchy. Many algorithms have been proposed. They differ based on: 1) the code granularity assumed by the reordering algorithm, and 2) the models used to guide code placement. In this paper we present a framework that provides accurate simulation and evaluation of code reordering algorithms on an out-of-order superscalar processor. Our approach allows both profile-guided and compile-time approaches to be simulated. Using a single simulation pass, different graph models are constructed and utilized during code placement. Various combinations of basic block/procedure reordering algorithms can be employed. We discuss the necessary modifications made to a detailed simulator of a processor in order to accurately simulate the optimized code layout. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1109/ISPASS.2000.842275 | ISPASS |
Keywords | Field | DocType |
optimized code layout,code granularity,accurate simulation,code placement,out-of-order superscalar processor,reordering algorithm,procedure reordering algorithm,memory hierarchy,available memory hierarchy,code reordering algorithm,code reordering,out of order,computational modeling,virtual machines,data structures,statistics,petroleum | Data structure,Virtual machine,Memory hierarchy,Computer science,Parallel computing,Basic block,Redundant code,Software,Out-of-order execution,Dead code | Conference |
ISBN | Citations | PageRank |
0-7803-6418-X | 1 | 0.35 |
References | Authors | |
9 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| J. Kalamatianos | 1 | 32 | 4.19 |
| David Kaeli | 2 | 1535 | 129.85 |