Name
Abstract | ||
|---|---|---|
Universal Pin Electronics represents a radical departure from normal tester architecture. It uses common electronics to create analog, parametric digital and functional digital stimulus and measurement capability in each tester channel. Key parameters include 100 MHz functional digital repetition rate, vector storage over one million bits, and analog/parametric digital stimulus/measurement capability to 20 MHz. For functional digital testing the UPE architecture results in advancements in overall tester throughput in addition to maximum repetition rate and vector (array) size. Key to these advancements is the architecture in general and the compaction/decompaction technique in particular. The discussion to follow will center on this unique process. |
Year | Venue | Keywords |
|---|---|---|
1984 | ITC | upe architecture result,parametric digital stimulus,measurement capability,maximum repetition rate,overall tester throughput,mhz functional digital repetition,key parameter,universal pin electronics,compaction technique,normal tester architecture,functional digital stimulus,tester channel |
Field | DocType | ISBN |
Architecture,Computer science,Communication channel,Electronic engineering,Parametric statistics,Electronics,Throughput,Computer hardware,Compaction | Conference | 0-8186-0548-0 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Philip C. Jackson | 1 | 5 | 2.14 |
| Gregory De Mare | 2 | 0 | 0.34 |
| Albert Esser | 3 | 0 | 0.34 |