Name
Abstract | ||
|---|---|---|
The digital design paradigm is in transition. We discuss on-chip programmable regulators to reduce power consumption; SERDES blocks to reduce the inter-block interconnections and small signal swing high-speed differential inputs and outputs to maximize performance in interconnect delay-dominated technologies. We need to build re-configurability and re-use of logic as an essential feature of device functionality. We need to adopt self-calibration mechanisms to solve the timing closure problem and find ways to reduce the cost of test by design. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICVD.2004.1261041 | VLSI Design |
Keywords | Field | DocType |
new paradigm,tobuild re-configurability,device functionality,timing closureproblem,serdes block,digital design paradigm,delay-dominated technology,programmable regulator,digital design,small signal swing high-speeddifferential,programmable controllers,calibration,chip,design methodology,design for testability,logic design,frequency,logic | Logic synthesis,Design for testing,Design paradigm,Computer science,Programmable logic array,Electronic engineering,Real-time computing,Integrated circuit design,Register-transfer level,SerDes,Timing closure | Conference |
ISBN | Citations | PageRank |
0-7695-2072-3 | 0 | 0.34 |
References | Authors | |
4 | 1 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Rajat Gupta | 1 | 9 | 2.67 |